Toshiba Unveils "SpursEngine": the Processor that inherits the Cell's architecture - Developed for video and recognition processing engines

Toshiba Unveils "SpursEngine": the Processor that inherits the Cell's architecture
Developed for video and recognition processing engines

Figure 1: SpursEngine implemented in a package

Manufactured using CMOS process technology with 65 nm design rule

Toshiba Semiconductor Company revealed technology overview of the stream processor "SpursEngine" that inherits the design architecture of Cell Broadband Engine (Cell/B.E.), a high performance processor used for "PlaySation 3 (PS3)" on September 20th in 2007 (Figure 1). Toshiba had so far admitted that it was developing a processor based on the Cell, and it disclosed the relevant technology for the first time. The main newly-developed SpursEngine is a video and recognition processing engine, aiming at consumer electronics and/or PCs as the major target markets. Toshiba assumes that SpursEngine is used with x86 processors and GPUs.

Figure 2: Block Diagrams of the Cell B.E. and SpursEngine

While the Cell/B.E. has eight SPEs, Toshiba reduced those on SpursEngine to four. Instead, SpursEngine has decoders/encoders for MPEG-2 and MPEG-4/AVC (H.264), supporting full HD (high definition) specification, for video processing.

There are four major differences from Cell/B.E. (Figure 2). First, Toshiba narrowed down the number of SPE (Synergistic Processor Element), a processor core to process multimedia data at high-speed; while the Cell has eight SPEs, SpursEngine has four. Secondly, encoders and decoders for MPEG-2 and MPEG-4/AVC(H.264), supporting full HD (high definition), are integrated on SpursEngine. By reducing the number of SPEs and instead adding proprietary hardware, encoders/decoders for video processing, it is possible to suppress the power consumption to a low level.

The third difference is that SpursEngine does NOT have PPE (PowerPC Element), the general-purpose processor integrated on the Cell/B.E. As a result, for example, a PC can use SpursEngine as the coprocessor for the x86 CPU to make the whole system compact. Moreover, the chip size can be smaller, and the power consumption lower.

Finally, the forth is the change in the external interface. Cell/B.E. adopted FlexIO from Rambus as the interface to the outside of the chip. While the maximum data transfer rate of FlexIO is high with the 6.4 G bit per second per terminal, PCI Express (4 G bit per second per lane) is used for North Bridge and South Bridge, chipsets of the PC. As a result, it was logical to adopt PCI Express as the external interface for SpursEngine, whose main target markets include the PC.

In addition, SpursEngine has some more features. For example, SpursEngine is equipped with the XDR interface and can connect to high-speed XDR DRAMs. The maximum data transfer rate between SpursEngine and XDR DRAM is 12.8GB/s. The manufacturing process uses a CMOS technology with 65 nm design rule. It is not using the SOI technology that is used for Cell/B.E. in order to lower the cost.

With the prototype chip manufactured this time, they have suppressed the operating frequency to 1.5 GHz, about half of that for the Cell Broadband Engine, to lower the power consumption. Consequently, the resultant power consumption is in the range of 10W level. Toshiba Semiconductor Company is planning to begin the sample shipment in earlier 2008 and then volume production at Oita fab. The company showcased the details of SpursEngine technology and demonstration used at the CEATEC Japan 2007 show (October 2nd - the 6th) at Makuhari Messe in Makuhari, Chiba.