Toshiba Semiconductor hosts SpursEngine Developers Forum - "Goal: to sell 6 million units or more over the next 3 years"
Toshiba Semiconductor hosts SpursEngine Developers Forum
"Goal: to sell 6 million units or more over the next 3 years"
Toshiba Semiconductor Company (hereafter, Toshiba) hosted SpursEngine Developers Forum 2008 on July 25th in Tokyo. SpursEngine is a stream processor Toshiba developed based on Cell Broadband Engine. This Forum was the first event in which SpursEngine's architecture, development environment, coding techniques, and products and services of the third parties were explained to developers who would design products equipped with SpursEngine.
First, Mr. Mitsuo Saito, Chief Fellow at Toshiba (Figure 1), gave a greeting speech and said, "We will get design wins in the PC market, accelerating stable supply chain and cost reduction. We want to sell 6 million units or more of SpursEngine over the next 3 years."
SpursEngine has been used in Toshiba's own AV notebook PC, Qosmio, which Toshiba began shipping around the end of July this year. Major features of SpursEngine, as a co-processor for PC's host CPU, are fast video compression, decompression, and other processing tasks. For example, upconversion from SD video to HD is a case in point; A SpursEngine would take in SD video encoded with MPEG-2 or H.264, decompress it with the hardware decoder, make it into HD using SPEs (Synergistic Processor Elements, same processor cores as on Cell Broadband Engine), and compress it again with the hardware encoder. Compared with a case in which a Core 2 Duo (at 2.8GHz) only is used, it is possible to execute about 10 times faster. This technology is equipped within Qosmio as Super Resolution. "We would like to build cooperative relationships with a variety of partner companies to widely provide visual/imaging solutions utilizing SpursEngine,"said Mr. Saito.
Secondly, Mr. Yoshio Masubuchi, Director of Advanced SoC Development Center at Toshiba, gave a presentation titled " SpursEngine Architecture and the Aims" (Figure 2). In the future, as terrestrial digital TV broadcasting, digital camcorder, Blu-ray Disc, and so on, become popular, HD contents will increase rapidly (Figure 3). HD contents will require six times as broad bandwidth as that for SD. However, "existing PCs can barely decode HD video in real-time and can hardly encode," pointed out Mr. Masubuchi. "Meanwhile, in order to perform video indexing and searching for continuously increasing video contents, advanced software processing will be essential to deal with flexible algorithms."
Mr. Masubuchi explained the architecture of SpursEngine upon analyzing such current situations. SpursEngine has four SPEs and hardware encoders and decoders for MPEG-2 and H.264, in addition. SPE is equipped with SIMD*1 operation instructions, 128 register files of 128 bits, and a 256-Kbyte local storage. One of the notable features is the on-chip local storage, instead of a cache memory. "With a large cache memory, the performance gain per transistor is small, and, moreover, cache miss penalty is too much," said Mr. Masubuchi.
SpursEngine, supposed to process massive data, has a powerful data transfer feature inside. It has on-chip DMA controller, enabling high-speed data transfer between the main memory and each local storage and among the local storages of the other SPEs. Also, the high-speed data bus connects the SPEs, decoder, and encoder as well.
Mr. Masubuchi expects the wave of stream processors arriving in the PC sector after 2008 (Figure 4). He forecasts stream processors will catch on as video processing engines in the future, just as GPUs for gaming appeared in the 1990s and became fixed as part of the PC architecture.
At the end of his presentation, Mr. Masubuchi showed the roadmap of SpursEngine and mentioned that SpursEngine II would be commercially available from 2009 to 2010.
*1: SIMD - Single Instruction Multiple Data
SIMD is a design architecture scheme, in which one single instruction performs multiple-data processing in parallel simultaneously
